The present invention relates generally to self time memories, and more specifically to a programmable self time circuit for controlling bit line separation in a memory during memory read access and the like.
In self time memories, the circuitry used to control bit line separation has typically consisted of a single bank of core cells tied to a common self time word line. Thus, the bit line separation is an inverse function of the number of self time core cells connected to the self time word line (STWL), or xe2x80x9cM-factorxe2x80x9d of the memory. For instance, FIG. 1 illustrates a self time circuit 100 wherein the self time word line xe2x80x9cSTWLxe2x80x9d 102 of the circuit 100 is connected to eight core cells 104. Thus, the circuit 100 illustrated would provide an M-factor of eight (8).
To modify the bit line separation, for example, to tune in a value of bit line separation that is sufficiently fast to accommodate the margin speed of the memory, the M-factor (i.e., number of core cells connected to the self-time word line) must be changed by either connecting or disconnecting core cells from the self time word line. Thus, as shown in FIG. 1, modification of the bit line separation by increasing the M-factor from eight (8) to nine (9) for the circuit 100 shown, requires that an additional core cell 106 be connected. However, connection or disconnection of core cells requires multiple mask changes making failure analysis or experimentation difficult and costly.
Consequently, it is desirable to provide a programmable self time circuit for controlling bit line separation in a memory when the memory is accessed, for example, during memory read access and the like, without the need to perform multiple masks.
Accordingly, the present invention is directed to a programmable self time circuit for controlling bit line separation in a memory when the memory is accessed, for example, during memory read access and the like. In exemplary embodiments, the self time circuit is comprised of multiple self time word lines, each of which is connected to at least one core cell of the memory for activating the cell. These self time word lines have enable signals that can either be programmed on/off, or can be externally controlled, allowing for variation of the amount of bit line separation developed during a memory access. In this manner, the number of possible bit line separations is limited only by the number of self time word lines and enables.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description oft he preferred embodiments given below, serve to explain the principles of the invention.